1. Field of the Invention
This invention relates to a computer and, more particularly, to a bus interface unit which maintains ownership of a central processing unit ("CPU") bus and therefore forestalls CPU-initiated cycles at times when the bus interface unit is sending a pre-defined number of snoop cycles to cache storage locations upon the CPU bus.
2. Description of the Related Art
Modem computers are called upon to execute instructions and transfer data at increasingly higher rates. Many computers employ CPUs which operate at clocking rates exceeding several hundred MHz, and further have multiple buses connected between the CPUs and numerous input/output devices. The buses may have dissimilar protocols depending on which devices they link. For example, a CPU local bus connected directly to the CPU preferably transfers data at a faster rate than a peripheral bus connected to slower input/output devices. A mezzanine bus may be used to connect devices arranged between the CPU local bus and the peripheral bus. The peripheral bus can be classified as, for example, an industry standard architecture ("ISA") bus, an enhanced ISA ("EISA") bus or a microchannel bus. The mezzanine bus can be classified as, for example, a peripheral component interconnect ("PCI") bus to which higher speed input/output devices can be connected.
Coupled between the various buses are bus interface units. According to somewhat known terminology, the bus interface unit coupled between the CPU bus and the PCI bus is often termed the "north bridge". Similarly, the bus interface unit between the PCI bus and the peripheral bus is often termed the "south bridge".
The north bridge, henceforth termed a bus interface unit, serves to link specific buses within the hierarchical bus architecture. Preferably, the bus interface unit couples data, address and control signals forwarded between the CPU local bus, the PCI bus and the memory bus. Accordingly, the bus interface unit may include various buffers and/or controllers situated at the interface of each bus linked by the interface unit. In addition, the bus interface unit may receive data from a dedicated graphics bus, and therefore may include an advanced graphics port ("AGP"). As a host device, the bus interface unit may be called upon to support both the PCI portion of the AGP (or graphics-dedicated transfers associated with PCI, henceforth is referred to as a graphics component interface, or "GCI"), as well as AGP extensions to the PCI protocol.
Mastership of the various buses is preferably orchestrated by several arbiters within the bus interface unit. For example, if a peripheral input/output device coupled to the PCI bus wishes to write data to the local memory, it must solicit mastership of the PCI bus before doing so. Once mastership is granted, the peripheral device can then forward the appropriate data to buffers or queues within the bus interface unit. That data may remain within the queues until another arbiter grants mastership of the memory bus. As a further example, before a CPU can read data from the local memory, the CPU must be granted mastership of the CPU bus before allowing data to be read from the memory bus.
Before a peripheral device can write data to local memory, it must not only arbitrate for the peripheral bus and the memory bus, but also must determine if the data within local memory is valid data. The process of determining where valid data exist, either within local memory or a cache storage location within the CPU, is often noted as a "snoop" operation. If the address written to in local memory is the same as an address of a cache storage location within the CPU, then it must be determined which address contains the most recent version of data. If cache within the CPU contains valid data (i.e., the most recent, modified, or dirty data) and data at the same address within system memory is not valid (i.e., is not the most recent, is invalid, or is stale data), then the CPU must writeback its valid data to the same address within system memory so that coherency can be maintained.
Once the address location within local memory is updated with valid data from the CPU cache, then the CPU cache storage location is marked with an "invalid" status bit while data transfers occur to the updated address location within the local memory. The process of writeback is beneficially used whenever a peripheral device desires to transfer data to an address location within system memory shared by one or more cache storage locations within one or more associated CPUs. A problem exists, however, in that the memory arbiter will automatically grant mastership of the memory bus to a CPU initiated cycle in lieu of a cycle derived from a peripheral device. In this fashion, the memory arbiter will allow faster CPU cycles to be serviced ahead of slower peripheral device cycles to ensure the CPU is not being starved for data and/or instructions. For example, if the memory arbiter holds off a CPU derived memory read cycle in favor of a write cycle arising from a peripheral device, then the CPU must wait a substantial amount of time until the slower PCI bus and/or queues within the bus interface unit can forward their contents to system memory. The amount of time needed to complete that transfer from the slower peripheral device and/or peripheral bus may unjustifiably stall the CPU, and execution units within the CPU.
Using the immediately preceding example, there may be instances in which data within the system memory should be written by a peripheral device before being read by the CPU. If, however, the peripheral device initiates a write cycle to memory and subsequently a CPU initiates a read cycle to that same location, then the memory arbiter will automatically grant priority to the CPU derived cycle and hold off the data transfer phase of the peripheral cycle. This will cause the CPU to read data from system memory which had not been properly updated by a write cycle from the peripheral device. An update of data from the peripheral device will therefore not be properly queued into the CPU. In other words, if the read cycle to a storage location by the CPU occurs before a write to that storage location by a peripheral device and after that address has been snooped out of the CPU, the computer system will be incoherent.
It would be desirable to implement an improved bus interface unit which can hold off CPU derived memory read cycles on the CPU bus until after the peripheral device is granted ownership of the memory bus. The improved bus interface unit could therefore assure that peripheral-derived data is written into the system memory before that data is read by the CPU. This effect is most profound when the data being read by the CPU is contingent on it originating from a peripheral device, and the read cycle request signal of the CPU occurs concurrent with or slightly after the peripheral write cycle request signal.
It would be further beneficial that multiple snoop cycles be dispatched upon the CPU bus by the bus interface unit before the CPU is granted mastership of the CPU bus. The desirous amount of snoop cycles occurring during ownership by the bus interface unit should vary depending on whether the computer system and/or application primarily involves peripheral bus transfers or CPU bus transfers.